1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a capacitor, and more particularly, to a method of manufacturing a capacitor electrode of a semiconductor integrated device represented by a storage apparatus and an information processor.
2. Description of the Background Art
With increase in integration degree of a DRAM (Dynamic Random Access Memory), a three-dimensional structure of a capacitor has been increasingly produced in order to secure sufficient capacitance thereof in limited space. Such a capacitor structure includes a fin type structure, a crown type (cylinder type) structure and the like.
Furthermore, a technique to form fine concaves and convexes at a surface of a storage node electrode (a lower electrode of a capacitor) formed of a polycrystalline silicon film so as to increase surface area has been proposed. Polycrystalline silicon therein is called polysilicon having a rough surface (hereinafter referred to as rough surface polysilicon) from the surface condition thereof.
Concaves and convexes are formed at a surface of a storage node by a technique described in, for example, H. Watanabe et al., "An Advanced Fabrication Technology of Hemispherical Grained (HSG) Poly-Si for High Capacitance Storage Electrodes", Extended Abstracts of the 1991 International Conference on Solid State Devices and Materials, Yokohama, 1991, pp. 478-480. A method of manufacturing a capacitor of a DRAM memory cell using this technique will now be described as a conventional method of manufacturing a semiconductor device.
FIGS. 11 to 15 are schematic cross sections sequentially showing the steps of a conventional method of manufacturing a semiconductor device having a capacitor.
First, referring to FIG. 11, a patterned gate electrode layer 7 is formed on a p type silicon substrate 1 with a gate insulating layer 5 therebetween. A pair of n.sup.- impurity regions 3a are formed at a prescribed distance away from each other so as to sandwich a region under gate electrode layer 7 therebetween, by ion implantation or the like using gate electrode layer 7 as a mask. An insulating layer 11 which covers gate electrode layer 7 is formed thereafter. A pair of n.sup.+ impurity regions 3b are formed at a surface of p type silicon substrate 1 by ion implantation or the like using insulating layer 11 as a mask. An n type source/drain regions 3 having an LDD (Lightly Doped Drain) structure is formed of n impurity region 3a and n.sup.+ impurity region 3b.
An MOS (Metal Oxide Semiconductor) is constituted by the pair of n type source/drain regions 3, gate insulating film 5 and gate electrode layer 7.
Referring to FIG. 12, an interlayer insulating layer 13 made of a silicon oxide film or the like is formed to cover an MOS transistor 10. A resist pattern 31 is formed on interlayer insulating layer 13 by normal photolithography technique. Interlayer insulating layer 13 is subject to anisotropic etching using resist pattern 31 as a mask. A contact hole 13a reaching to a partial surface of n type source/drain region 3 is formed by this anisotropic etching. Resist pattern 31 is then removed.
Referring to FIG. 13, a rough surface polysilicon layer 15a is formed under the conditions in the above article so as to be electrically connected to n type source/drain region 3 through contact hole 13a and to extend over interlayer insulating layer 13. More specifically, the rough surface polysilicon is formed by an LPCVD (Low Pressure Chemical Vapor Deposition) method using gas containing 20% silane (SiH.sub.4) at 1.0 Torr and a temperature of 590.degree. C.
Referring to FIG. 14, a resist pattern 33 having a desired shape is formed on rough surface polysilicon 15a by normal photolithography technique. Rough surface polysilicon 15a is subject to anisotropic etching using this resist pattern 33 as a mask.
Referring to FIG. 15, the rough surface polysilicon is patterned by this anisotropic etching. Thus, a storage node (lower electrode) 15 which is electrically connected to n type source/drain region 3 through contact hole 13a and extends on interlayer insulating layer 13 is formed. A capacitor insulating layer 17 is formed to cover storage node 15. Since capacitor insulating layer 17 is formed relatively thin, a surface of capacitor insulating layer 17 on storage node 15 has concaves and convexes which reflect the shape of concaves and convexes at the surface of storage node 15. A cell plate (upper electrode) 19 is formed to be opposite to storage node 15 through capacitor insulating layer 17.
A capacitor 20 is constituted by storage node 15, capacitor insulating layer 17 and cell plate 19.
Thus, a DRAM memory cell with a single-transistor/single-capacitor structure formed of MOS transistor 10 and capacitor 20 is completed.
Since the storage node formed as described above has concaves and convexes at a surface thereof, this storage node is characterized in that area in which storage node 15 and cell plate 19 are opposite to each other, per area occupied by a capacitor can be increased.
It is known, however, that as to a property of a thin capacitor insulating layer formed on a rough surface polysilicon, leak current between capacitor electrodes is somewhat increased as shown in FIG. 16 compared to the case of a polysilicon layer having a flat surface.
A method of measuring leak current mentioned above will now be described.
FIG. 17 is a cross section showing a structure of a sample used to measure leak current. Referring to FIG. 17, an interlayer insulating layer 13 having a contact hole 13a is formed on a silicon substrate 1. A storage node 15 is formed to be connected to silicon substrate 1 through contact hole 13a. A cell plate 19 is formed to be opposite to storage node 15 with a capacitor insulating layer 17 therebetween.
With cell plate 19 used as one electrode and silicon substrate 1 as the other electrode, leak current (the ordinate of FIG. 16) with respect to voltage (the abscissa of FIG. 16) applied therebetween was measured.
In addition, respective voltage resistances of capacitors in which a polysilicon layer having a relatively flat surface, a polysilicon layer having a surface with relatively rounded tips of convexes, and a polysilicon layer having a surface with relatively acute-angled tips of convexes were respectively used as a storage node 15 were measured under the same conditions. As a result, voltage resistance was 3.17 V for a capacitor using a polysilicon layer having a relatively flat surface, 2.8 V for a capacitor using a polysilicon layer having a surface with relatively rounded tips of convexes, and 2.29 V for a capacitor using a polysilicon layer having a surface with relatively acute-angled tips of convexes.
Consequently, it has been found that acuter-angled (more needle-like) tips of convexes at a surface having concaves and convexes cause larger increase (degradation) in leak current. It can be considered that this increase in leak current results from concentration of an electric field caused by a shape of a surface of polysilicon. More specifically, it can be considered that acute-angled tips of convexes tend to facilitate concentration of an electric field on those tips, causing leak current.